# Makefile for simulink the project
PLATFORM = LINUX64
waveform = $(TEST_NAME).fsdb

PROJECT_PATH := /home/yian/Desktop/my_prj/rtl
export PROJECT_PATH

FILE_LIST = filelist.f
VHDL_FILE_LIST = vhdl_filelist.f
TEST_NAME = aru_reduce
TOP_MODULE = aru_reduce_tb

all: clean comp sim

comp:
	vhdlan -full64 -vhdl08 -work work -f $(VHDL_FILE_LIST) -l vhdlan.log
	
	vlogan -full64 -sverilog \
	    -timescale=1ns/1ps \
	    -debug_acc+all \
	    -kdb \
	    -work work \
	    -f $(FILE_LIST) \
	    -l vlogan.log
	
	vcs -full64 \
	    -debug_acc+all \
	    -kdb \
	    -LDFLAGS -rdynamic \
	    -P $(VERDI_HOME)/share/PLI/VCS/$(PLATFORM)/novas.tab \
	    $(VERDI_HOME)/share/PLI/VCS/$(PLATFORM)/pli.a \
	    -L work \
	    -top $(TOP_MODULE) \
	    -o simv \
	    -l vcs_elab.log

sim:
	./simv +fsdb+autoflush -l vcs_sim.log

verdi:
	verdi -kdb simv.daidir -ssf $(waveform) &

clean:
	@rm -rf csrc DVEfiles simv simv.daidir ucli.key novas* VCS* *dat verdiLog *.log verdi_config_file work.lib++